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wire [7:0]    irq_enable;
reg [7:0]    irq_act;
   
   



`VARIANT`MB
#(.IRQ_ENABLE_RST(IRQ_MODE))
vic_micro_reg
(   
        .clk               ( clk          ),
        .reset             ( reset        ),
        .enable            ( enable       ),
        .cs                ( cs           ),              
        .wr                ( wr           ),
        .rd                ( rd           ),
        .byte_lanes        ( 1'b1         ),
        .addr              ( addr         ),
        .wdata             ( wdata        ),
        .rdata             ( rdata        ),
        .int_in_cs         (              ),
        .int_in_dec        (              ),
        .irq_enable_cs     (              ),
        .irq_enable_dec    (              ),
        .irq_enable_wr_0   (              ),
        .irq_act_cs        (              ),
        .irq_act_dec       (              ),
        .irq_vec_cs        (              ),
        .irq_vec_dec       (              ),
        .int_in_rdata      ( int_in       ),
        .irq_act_rdata     ( irq_act      ),
        .irq_vec_rdata     ( vector       ),
        .irq_enable        ( irq_enable   ),
        .next_irq_enable   ( irq_enable   ),
        .irq_enable_rdata  ( irq_enable   )
);
   





always@(posedge clk)
if (reset) 
   begin
   irq_act     <= 8'h00;
   irq_out     <= 1'b0;
   end
else 
  begin
   irq_act     <=  irq_enable & int_in;
   irq_out     <=  | irq_act;
   end
  


always@(posedge clk)
if (reset) 
                   vector  <= VEC_NONE;
  
else 
if(irq_act[0])     vector  <= VEC_00;
else 
if(irq_act[1])     vector  <= VEC_01;
else 
if(irq_act[2])     vector  <= VEC_02;
else 
if(irq_act[3])     vector  <= VEC_03;
else 
if(irq_act[4])     vector  <= VEC_04;
else 
if(irq_act[5])     vector  <= VEC_05;
else 
if(irq_act[6])     vector  <= VEC_06;
else 
if(irq_act[7])     vector  <= VEC_07;
else 
                   vector  <= VEC_NONE;