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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [disp_io_def.sch] - Rev 135
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v 20100214 1
C 1700 300 1 0 0 in_port_vector.sym
{
T 1700 300 5 10 1 1 0 6 1 1
refdes=sw_pad_in[7:0]
}
C 1700 700 1 0 0 in_port_vector.sym
{
T 1700 700 5 10 1 1 0 6 1 1
refdes=btn_pad_in[3:0]
}
C 1700 1100 1 0 0 in_port_vector.sym
{
T 1700 1100 5 10 1 1 0 6 1 1
refdes=PosL[7:0]
}
C 1700 1500 1 0 0 in_port_vector.sym
{
T 1700 1500 5 10 1 1 0 6 1 1
refdes=PosD[15:0]
}
C 1700 1900 1 0 0 in_port.sym
{
T 1700 1900 5 10 1 1 0 6 1 1
refdes=reset
}
C 1700 2300 1 0 0 in_port.sym
{
T 1700 2300 5 10 1 1 0 6 1 1
refdes=enable
}
C 1700 2700 1 0 0 in_port.sym
{
T 1700 2700 5 10 1 1 0 6 1 1
refdes=clk
}
C 4600 300 1 0 0 out_port_vector.sym
{
T 5600 300 5 10 1 1 0 0 1 1
refdes=seg_pad_out[6:0]
}
C 4600 700 1 0 0 out_port_vector.sym
{
T 5600 700 5 10 1 1 0 0 1 1
refdes=led_pad_out[7:0]
}
C 4600 1100 1 0 0 out_port_vector.sym
{
T 5600 1100 5 10 1 1 0 0 1 1
refdes=an_pad_out[3:0]
}
C 4600 1500 1 0 0 out_port_vector.sym
{
T 5600 1500 5 10 1 1 0 0 1 1
refdes=PosS[7:0]
}
C 4600 1900 1 0 0 out_port_vector.sym
{
T 5600 1900 5 10 1 1 0 0 1 1
refdes=PosB[3:0]
}
C 4600 2300 1 0 0 out_port.sym
{
T 5600 2300 5 10 1 1 0 0 1 1
refdes=dp_pad_out
}