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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [micro_bus_exp9.sch] - Rev 135
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v 20100214 1
C 2100 300 1 0 0 in_port_vector.sym
{
T 2100 300 5 10 1 1 0 6 1 1
refdes=wdata_in[7:0]
}
C 2100 700 1 0 0 in_port_vector.sym
{
T 2100 700 5 10 1 1 0 6 1 1
refdes=mas_8_rdata_in[7:0]
}
C 2100 1100 1 0 0 in_port_vector.sym
{
T 2100 1100 5 10 1 1 0 6 1 1
refdes=mas_7_rdata_in[7:0]
}
C 2100 1500 1 0 0 in_port_vector.sym
{
T 2100 1500 5 10 1 1 0 6 1 1
refdes=mas_6_rdata_in[7:0]
}
C 2100 1900 1 0 0 in_port_vector.sym
{
T 2100 1900 5 10 1 1 0 6 1 1
refdes=mas_5_rdata_in[7:0]
}
C 2100 2300 1 0 0 in_port_vector.sym
{
T 2100 2300 5 10 1 1 0 6 1 1
refdes=mas_4_rdata_in[7:0]
}
C 2100 2700 1 0 0 in_port_vector.sym
{
T 2100 2700 5 10 1 1 0 6 1 1
refdes=mas_3_rdata_in[7:0]
}
C 2100 3100 1 0 0 in_port_vector.sym
{
T 2100 3100 5 10 1 1 0 6 1 1
refdes=mas_2_rdata_in[7:0]
}
C 2100 3500 1 0 0 in_port_vector.sym
{
T 2100 3500 5 10 1 1 0 6 1 1
refdes=mas_1_rdata_in[7:0]
}
C 2100 3900 1 0 0 in_port_vector.sym
{
T 2100 3900 5 10 1 1 0 6 1 1
refdes=mas_0_rdata_in[7:0]
}
C 2100 4300 1 0 0 in_port_vector.sym
{
T 2100 4300 5 10 1 1 0 6 1 1
refdes=addr_in[7:0]
}
C 2100 4700 1 0 0 in_port.sym
{
T 2100 4700 5 10 1 1 0 6 1 1
refdes=wr_in
}
C 2100 5100 1 0 0 in_port.sym
{
T 2100 5100 5 10 1 1 0 6 1 1
refdes=reset
}
C 2100 5500 1 0 0 in_port.sym
{
T 2100 5500 5 10 1 1 0 6 1 1
refdes=rd_in
}
C 2100 5900 1 0 0 in_port.sym
{
T 2100 5900 5 10 1 1 0 6 1 1
refdes=enable
}
C 2100 6300 1 0 0 in_port.sym
{
T 2100 6300 5 10 1 1 0 6 1 1
refdes=cs_in
}
C 2100 6700 1 0 0 in_port.sym
{
T 2100 6700 5 10 1 1 0 6 1 1
refdes=clk
}
C 5400 300 1 0 0 out_port_vector.sym
{
T 6400 300 5 10 1 1 0 0 1 1
refdes=rdata_out[15:0]
}
C 5400 700 1 0 0 out_port_vector.sym
{
T 6400 700 5 10 1 1 0 0 1 1
refdes=mas_8_wdata_out[7:0]
}
C 5400 1100 1 0 0 out_port_vector.sym
{
T 6400 1100 5 10 1 1 0 0 1 1
refdes=mas_8_addr_out[3:0]
}
C 5400 1500 1 0 0 out_port_vector.sym
{
T 6400 1500 5 10 1 1 0 0 1 1
refdes=mas_7_wdata_out[7:0]
}
C 5400 1900 1 0 0 out_port_vector.sym
{
T 6400 1900 5 10 1 1 0 0 1 1
refdes=mas_7_addr_out[3:0]
}
C 5400 2300 1 0 0 out_port_vector.sym
{
T 6400 2300 5 10 1 1 0 0 1 1
refdes=mas_6_wdata_out[7:0]
}
C 5400 2700 1 0 0 out_port_vector.sym
{
T 6400 2700 5 10 1 1 0 0 1 1
refdes=mas_6_addr_out[3:0]
}
C 5400 3100 1 0 0 out_port_vector.sym
{
T 6400 3100 5 10 1 1 0 0 1 1
refdes=mas_5_wdata_out[7:0]
}
C 5400 3500 1 0 0 out_port_vector.sym
{
T 6400 3500 5 10 1 1 0 0 1 1
refdes=mas_5_addr_out[3:0]
}
C 5400 3900 1 0 0 out_port_vector.sym
{
T 6400 3900 5 10 1 1 0 0 1 1
refdes=mas_4_wdata_out[7:0]
}
C 5400 4300 1 0 0 out_port_vector.sym
{
T 6400 4300 5 10 1 1 0 0 1 1
refdes=mas_4_addr_out[3:0]
}
C 5400 4700 1 0 0 out_port_vector.sym
{
T 6400 4700 5 10 1 1 0 0 1 1
refdes=mas_3_wdata_out[7:0]
}
C 5400 5100 1 0 0 out_port_vector.sym
{
T 6400 5100 5 10 1 1 0 0 1 1
refdes=mas_3_addr_out[3:0]
}
C 5400 5500 1 0 0 out_port_vector.sym
{
T 6400 5500 5 10 1 1 0 0 1 1
refdes=mas_2_wdata_out[7:0]
}
C 5400 5900 1 0 0 out_port_vector.sym
{
T 6400 5900 5 10 1 1 0 0 1 1
refdes=mas_2_addr_out[3:0]
}
C 5400 6300 1 0 0 out_port_vector.sym
{
T 6400 6300 5 10 1 1 0 0 1 1
refdes=mas_1_wdata_out[7:0]
}
C 5400 6700 1 0 0 out_port_vector.sym
{
T 6400 6700 5 10 1 1 0 0 1 1
refdes=mas_1_addr_out[3:0]
}
C 5400 7100 1 0 0 out_port_vector.sym
{
T 6400 7100 5 10 1 1 0 0 1 1
refdes=mas_0_wdata_out[7:0]
}
C 5400 7500 1 0 0 out_port_vector.sym
{
T 6400 7500 5 10 1 1 0 0 1 1
refdes=mas_0_addr_out[3:0]
}
C 5400 7900 1 0 0 out_port.sym
{
T 6400 7900 5 10 1 1 0 0 1 1
refdes=wait_out
}
C 5400 8300 1 0 0 out_port.sym
{
T 6400 8300 5 10 1 1 0 0 1 1
refdes=mas_8_wr_out
}
C 5400 8700 1 0 0 out_port.sym
{
T 6400 8700 5 10 1 1 0 0 1 1
refdes=mas_8_rd_out
}
C 5400 9100 1 0 0 out_port.sym
{
T 6400 9100 5 10 1 1 0 0 1 1
refdes=mas_8_cs_out
}
C 5400 9500 1 0 0 out_port.sym
{
T 6400 9500 5 10 1 1 0 0 1 1
refdes=mas_7_wr_out
}
C 5400 9900 1 0 0 out_port.sym
{
T 6400 9900 5 10 1 1 0 0 1 1
refdes=mas_7_rd_out
}
C 5400 10300 1 0 0 out_port.sym
{
T 6400 10300 5 10 1 1 0 0 1 1
refdes=mas_7_cs_out
}
C 5400 10700 1 0 0 out_port.sym
{
T 6400 10700 5 10 1 1 0 0 1 1
refdes=mas_6_wr_out
}
C 5400 11100 1 0 0 out_port.sym
{
T 6400 11100 5 10 1 1 0 0 1 1
refdes=mas_6_rd_out
}
C 5400 11500 1 0 0 out_port.sym
{
T 6400 11500 5 10 1 1 0 0 1 1
refdes=mas_6_cs_out
}
C 5400 11900 1 0 0 out_port.sym
{
T 6400 11900 5 10 1 1 0 0 1 1
refdes=mas_5_wr_out
}
C 5400 12300 1 0 0 out_port.sym
{
T 6400 12300 5 10 1 1 0 0 1 1
refdes=mas_5_rd_out
}
C 5400 12700 1 0 0 out_port.sym
{
T 6400 12700 5 10 1 1 0 0 1 1
refdes=mas_5_cs_out
}
C 5400 13100 1 0 0 out_port.sym
{
T 6400 13100 5 10 1 1 0 0 1 1
refdes=mas_4_wr_out
}
C 5400 13500 1 0 0 out_port.sym
{
T 6400 13500 5 10 1 1 0 0 1 1
refdes=mas_4_rd_out
}
C 5400 13900 1 0 0 out_port.sym
{
T 6400 13900 5 10 1 1 0 0 1 1
refdes=mas_4_cs_out
}
C 5400 14300 1 0 0 out_port.sym
{
T 6400 14300 5 10 1 1 0 0 1 1
refdes=mas_3_wr_out
}
C 5400 14700 1 0 0 out_port.sym
{
T 6400 14700 5 10 1 1 0 0 1 1
refdes=mas_3_rd_out
}
C 5400 15100 1 0 0 out_port.sym
{
T 6400 15100 5 10 1 1 0 0 1 1
refdes=mas_3_cs_out
}
C 5400 15500 1 0 0 out_port.sym
{
T 6400 15500 5 10 1 1 0 0 1 1
refdes=mas_2_wr_out
}
C 5400 15900 1 0 0 out_port.sym
{
T 6400 15900 5 10 1 1 0 0 1 1
refdes=mas_2_rd_out
}
C 5400 16300 1 0 0 out_port.sym
{
T 6400 16300 5 10 1 1 0 0 1 1
refdes=mas_2_cs_out
}
C 5400 16700 1 0 0 out_port.sym
{
T 6400 16700 5 10 1 1 0 0 1 1
refdes=mas_1_wr_out
}
C 5400 17100 1 0 0 out_port.sym
{
T 6400 17100 5 10 1 1 0 0 1 1
refdes=mas_1_rd_out
}
C 5400 17500 1 0 0 out_port.sym
{
T 6400 17500 5 10 1 1 0 0 1 1
refdes=mas_1_cs_out
}
C 5400 17900 1 0 0 out_port.sym
{
T 6400 17900 5 10 1 1 0 0 1 1
refdes=mas_0_wr_out
}
C 5400 18300 1 0 0 out_port.sym
{
T 6400 18300 5 10 1 1 0 0 1 1
refdes=mas_0_rd_out
}
C 5400 18700 1 0 0 out_port.sym
{
T 6400 18700 5 10 1 1 0 0 1 1
refdes=mas_0_cs_out
}