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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [verilog/] [copyright.v] - Rev 134
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/**********************************************************************/ /* */ /* ------- */ /* / SOC \ */ /* / GEN \ */ /* / COMPONENT \ */ /* ============== */ /* | | */ /* |____________| */ /* */ /* display io interface for Digilent FPGA boards */ /* */ /* */ /* Author(s): */ /* - John Eaton, jt_eaton@opencores.org */ /* */ /**********************************************************************/ /* */ /* Copyright (C) <2010> <Ouabache Design Works> */ /* */ /* This source file may be used and distributed without */ /* restriction provided that this copyright statement is not */ /* removed from the file and that any derivative work contains */ /* the original copyright notice and the associated disclaimer. */ /* */ /* This source file is free software; you can redistribute it */ /* and/or modify it under the terms of the GNU Lesser General */ /* Public License as published by the Free Software Foundation; */ /* either version 2.1 of the License, or (at your option) any */ /* later version. */ /* */ /* This source is distributed in the hope that it will be */ /* useful, but WITHOUT ANY WARRANTY; without even the implied */ /* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ /* PURPOSE. See the GNU Lesser General Public License for more */ /* details. */ /* */ /* You should have received a copy of the GNU Lesser General */ /* Public License along with this source; if not, download it */ /* from http://www.opencores.org/lgpl.shtml */ /* */ /**********************************************************************/
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