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   reg                        del_rd;
   reg     [1:0]                   del_wr;


   
   always@(posedge clk)
   if(!(stb))         del_wr  <= 2'b00;
   else               del_wr  <= {del_wr[0],wr};
   

   always@(posedge clk)
   if(!(stb))         del_rd  <= 1'b0;
   else               del_rd  <= rd;   

   
always@(*)     memadr_out       =  addr;
always@(*)     memdb_out        = wdata;
always@(*)     memdb_oe         = wr && (|cs);   

   
always@(posedge clk)
if(reset)
  begin
     ramadv_n_out    <= 1'b0; 
     ramcre_out      <= 1'b0;   
     flashcs_n_out   <= 1'b1;
     flashrp_n_out   <= 1'b1;
     ramclk_out      <= 1'b0;
  end

else

  begin
     ramadv_n_out    <= 1'b0;
     ramcre_out      <= 1'b0;     
     ramclk_out      <= 1'b0;
     flashcs_n_out   <= !  cs[1];
     flashrp_n_out   <= flashrp_n_out;    
  end // else: !if(reset)




always@(posedge clk)
if(reset)
  begin
     wait_out        <= 1'b1;   
     memoe_n_out     <= 1'b1;   
     memwr_n_out     <= 1'b1;
     ramcs_n_out     <= 1'b1;  
     ramlb_n_out     <= 1'b1;  
     ramub_n_out     <= 1'b1;  
  end

else

  begin
     wait_out        <= 1'b0;   
     memoe_n_out     <= !(rd && (|cs));
     memwr_n_out     <= !(wr &&   ( del_wr== 'b00)  && (|cs) ) ;
     ramcs_n_out     <= ! cs[0];
     ramlb_n_out     <= !(lb && (|cs));
     ramub_n_out     <= !(ub && (|cs));
  end
   


assign   rdata =   memdb_in;