URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [testbenches/] [verilog/] [tb.ext] - Rev 131
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assign stb =|cs;
wire [15:0] memdb_io;
wire addr_0;
micro_bus16_model_def
bus16
(
.clk ( clk ),
.reset ( reset ),
.addr ( {addr,addr_0} ),
.wdata ( wdata ),
.cs ( cs ),
.rd ( rd ),
.wr ( wr ),
.ub ( ub ),
.lb ( lb ),
.rdata ( rdata )
);
cde_pad_se_dig #(.WIDTH(16))
memdb_buff
(
.pad_out ( memdb_out ),
.pad_oe ( memdb_oe ),
.pad_in ( memdb_in ),
.PAD ( memdb_io )
);
pullup pu_ramwait ( ramwait_n );
mt45w8mw12_def
psram (
.clk ( ramclk_out ),
.adv_n ( ramadv_n_out ),
.cre ( ramcre_out ),
.o_wait ( ramwait_n ),
.ce_n ( ramcs_n_out ),
.oe_n ( memoe_n_out ),
.we_n ( memwr_n_out ),
.lb_n ( ramlb_n_out ),
.ub_n ( ramub_n_out ),
.addr ( memadr_out ),
.dq ( memdb_io )
);
assign STOP = 1'b0;
assign BAD = 1'b0;
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