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assign enable     = ~( ext_mem_wait || io_reg_wait  );



/*   CH0   */

reg mem_cs_r;
        

always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH0_BITS] == CH0_MATCH)      mem_cs         = 1'b1;
 else                                              mem_cs         = 1'b0;
 end 


always@(posedge clk)

begin
     mem_cs_r  <=     mem_cs;
end 

   
assign mem_addr   = addr_in;
assign mem_rd     = rd_in;
assign mem_wr     = wr_in;
assign mem_wdata  = {wdata_in,wdata_in};






/*   CH1   */

reg data_cs_r;

always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH1_BITS] == CH1_MATCH)   data_cs           = 1'b1;
 else                                           data_cs           = 1'b0;
 end 

always@(posedge clk)
begin
     data_cs_r  <=     data_cs;
end 

assign data_addr            = addr_in[ADD-CH1_BITS-1:1];
assign data_rd              = rd_in;
assign data_wr              = wr_in;
assign data_wdata           = {wdata_in,wdata_in};
assign data_be[0]           = !addr_in[0];
assign data_be[1]           =  addr_in[0];


/*   CH2   */
reg io_reg_cs_r;

always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH2_BITS] == CH2_MATCH)   io_reg_cs           = 1'b1;
 else                               io_reg_cs           = 1'b0;
 end 

always@(posedge clk)

begin
     io_reg_cs_r  <=     io_reg_cs;
end 


assign io_reg_addr            = addr_in[ADD-CH2_BITS-1:0];
assign io_reg_rd              = rd_in;
assign io_reg_wr              = wr_in;
assign io_reg_wdata           = wdata_in;

/*   CH3   */

reg ext_mem_cs_r;

always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH3_BITS] == CH3_MATCH)     ext_mem_cs            = 1'b1;
 else                                             ext_mem_cs            = 1'b0;
 end


always@(posedge clk)

begin
     ext_mem_cs_r  <=     ext_mem_cs;
end 

assign ext_mem_addr            = addr_in[ADD-CH3_BITS-1:0];
assign ext_mem_rd              = rd_in;
assign ext_mem_wr              = wr_in;
assign ext_mem_wdata           = {wdata_in,wdata_in};


/*   CH4   */

reg prog_rom_mem_cs_r;


always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH4_BITS] == CH4_MATCH)   prog_rom_mem_cs          = 1'b1;
 else                                           prog_rom_mem_cs          = 1'b0;
 end

always@(posedge clk)

begin
     prog_rom_mem_cs_r  <=     prog_rom_mem_cs;
end 
assign prog_rom_mem_addr            = addr_in[ADD-CH4_BITS-1:0];
assign prog_rom_mem_rd              = rd_in;
assign prog_rom_mem_wr              = wr_in;
assign prog_rom_mem_wdata           = {wdata_in,wdata_in};

/*   CH5   */


reg sh_prog_rom_mem_cs_r;

always@(addr_in)
 begin
 if(addr_in[ADD-1:ADD-CH5_BITS] == CH5_MATCH)  sh_prog_rom_mem_cs         = 1'b1;  
 else                                          sh_prog_rom_mem_cs         = 1'b0;        
 end 


always@(posedge clk)

begin
     sh_prog_rom_mem_cs_r  <=     sh_prog_rom_mem_cs;
end 

assign sh_prog_rom_mem_addr            = addr_in[ADD-CH5_BITS-1:0];
assign sh_prog_rom_mem_rd              = rd_in;
assign sh_prog_rom_mem_wr              = wr_in;
assign sh_prog_rom_mem_wdata           = {wdata_in,wdata_in};








always@(*)
if ( mem_cs_r )                   rdata_out = mem_rdata;
else
if ( data_cs_r )                  rdata_out = data_rdata;
else
if ( prog_rom_mem_cs_r )          rdata_out = prog_rom_mem_rdata;
else
if ( io_reg_cs_r )                rdata_out = io_reg_rdata;
else
if ( sh_prog_rom_mem_cs_r )       rdata_out = sh_prog_rom_mem_rdata;
else                              rdata_out = ext_mem_rdata;