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 reg mem_cs_r;
        

always@(*)
 begin
 if(addr_in[15:8] == 8'h00)      mem_cs         = 1'b1;
 else                            mem_cs         = 1'b0;
 end 


always@(posedge clk)

begin
     mem_cs_r  <=     mem_cs;
end 

   
assign mem_addr   = addr_in;
assign mem_rd     = rd_in;
assign mem_wr     = wr_in;
assign mem_wdata  = {wdata_in,wdata_in};
assign enable     = ~( ext_mem_wait || io_reg_wait  );






reg data_cs_r;

always@(*)
 begin
 if(addr_in[15:12] == 4'b0000)   data_cs           = 1'b1;
 else                            data_cs           = 1'b0;
 end 

always@(posedge clk)

begin
     data_cs_r  <=     data_cs;
end 

assign data_addr            = addr_in[11:1];
assign data_rd              = rd_in;
assign data_wr              = wr_in;
assign data_wdata           = {wdata_in,wdata_in};
assign data_be[0]           = !addr_in[0];
assign data_be[1]           =  addr_in[0];







reg io_reg_cs_r;

always@(*)
 begin
 if(addr_in[15:8] == 8'b10000000)   io_reg_cs           = 1'b1;
 else                               io_reg_cs           = 1'b0;
 end 

always@(posedge clk)

begin
     io_reg_cs_r  <=     io_reg_cs;
end 


assign io_reg_addr            = addr_in[7:0];
assign io_reg_rd              = rd_in;
assign io_reg_wr              = wr_in;
assign io_reg_wdata           = wdata_in;







reg ext_mem_cs_r;

always@(*)
 begin
 if(addr_in[15:14] == 2'b01)     ext_mem_cs            = 1'b1;
 else                            ext_mem_cs            = 1'b0;
 end


always@(posedge clk)

begin
     ext_mem_cs_r  <=     ext_mem_cs;
end 



assign ext_mem_addr            = addr_in[13:0];
assign ext_mem_rd              = rd_in;
assign ext_mem_wr              = wr_in;
assign ext_mem_wdata           = {wdata_in,wdata_in};





reg prog_rom_mem_cs_r;


always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)   prog_rom_mem_cs          = 1'b1;
 else                            prog_rom_mem_cs          = 1'b0;
 end

always@(posedge clk)

begin
     prog_rom_mem_cs_r  <=     prog_rom_mem_cs;
end 


assign prog_rom_mem_addr            = addr_in[11:0];
assign prog_rom_mem_rd              = rd_in;
assign prog_rom_mem_wr              = wr_in;
assign prog_rom_mem_wdata           = {wdata_in,wdata_in};









reg sh_prog_rom_mem_cs_r;


always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)  sh_prog_rom_mem_cs         = 1'b1;  
 else                           sh_prog_rom_mem_cs         = 1'b0;        
 end 


always@(posedge clk)

begin
     sh_prog_rom_mem_cs_r  <=     sh_prog_rom_mem_cs;
end 

assign sh_prog_rom_mem_addr            = addr_in[11:0];
assign sh_prog_rom_mem_rd              = rd_in;
assign sh_prog_rom_mem_wr              = wr_in;
assign sh_prog_rom_mem_wdata           = {wdata_in,wdata_in};








always@(*)
if ( mem_cs_r )                   rdata_out = mem_rdata;
else
if ( data_cs_r )                  rdata_out = data_rdata;
else
if ( prog_rom_mem_cs_r )          rdata_out = prog_rom_mem_rdata;
else
if ( io_reg_cs_r )                rdata_out = io_reg_rdata;
else
if ( sh_prog_rom_mem_cs_r )       rdata_out = sh_prog_rom_mem_rdata;
else                              rdata_out = ext_mem_rdata;