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reg [4:0] mem_cs_r;


 always@(posedge clk)     mem_cs_r  <=     mem_cs;


always@(*)
 begin
 if(addr_in[15:12] == 4'b0000)     mem_cs[0]         = 1'b1;
 else                             mem_cs[0]         = 1'b0;
 end 

always@(*)
 begin
 if(addr_in[15:12] == 4'b1111)   mem_cs[1]         = 1'b1;  
 else                             mem_cs[1]         = 1'b0;    
 end


always@(*)
 begin
 if(addr_in[15:12] == 4'b1100)   mem_cs[2]         = 1'b1;  
 else                            mem_cs[2]         = 1'b0;        
 end 


always@(*)
 begin
 if(addr_in[15:12] == 4'b1000)  mem_cs[3]         = 1'b1;
 else                            mem_cs[3]         = 1'b0;
 end 



   
always@(*)
 begin
 if(addr_in[15:14] == 2'b01)  mem_cs[4]          = 1'b1;
 else                            mem_cs[4]          = 1'b0;
 end









   
always@(*)
if ( mem_cs_r[0] ) rdata_out = mem_rdata[7:0];
else
if ( mem_cs_r[1] ) rdata_out = mem_rdata[15:8];
else
if ( mem_cs_r[2] ) rdata_out = mem_rdata[23:16];
else
if ( mem_cs_r[3] ) rdata_out = mem_rdata[31:24];
else               rdata_out = addr_in[0]?mem_rdata[47:40]:mem_rdata[39:32];
   




assign mem_addr   =  addr_in;
assign mem_rd     =  rd_in;
assign mem_wr     =  wr_in;
assign mem_wdata  = {wdata_in,wdata_in};
assign enable     = ~(|mem_wait);