OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_def.xml] - Rev 133

Go to most recent revision | Compare with Previous | Blame | View Log 

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>logic</spirit:library>
<spirit:name>micro_bus</spirit:name>
<spirit:version>def</spirit:version>  <spirit:configuration>default</spirit:configuration>  



<spirit:busInterfaces>

 <spirit:busInterface><spirit:name>slave_clk</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>clk</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>slave_reset</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>reset</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>reset</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>master_enable</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="enable" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="enable" spirit:version="rtl"/>
  <spirit:master/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>enable</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>enable</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>cpu</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:slave>
  <spirit:memoryMapRef spirit:memoryMapRef="cpu"/>
  <spirit:bridge spirit:masterRef="ext_mem"          spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="io_reg"           spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="data"             spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="prog_rom_mem"     spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="sh_prog_rom_mem"  spirit:opaque="true"/>
  </spirit:slave>

    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>addr_in</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rdata_out</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>



      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wdata_in</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wr_in</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rd_in</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>



    </spirit:portMaps>
 </spirit:busInterface>



 <spirit:busInterface><spirit:name>mem</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master> <spirit:addressSpaceRef spirit:addressSpaceRef= "mem" /></spirit:master>


    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wait</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_wait</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mem_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





 <spirit:busInterface><spirit:name>data</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>

  <spirit:master> <spirit:addressSpaceRef spirit:addressSpaceRef= "data" />        </spirit:master>

    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>11</spirit:left><spirit:right>1</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>be</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_be</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>data_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>




 <spirit:busInterface><spirit:name>io_reg</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>

  <spirit:master> <spirit:addressSpaceRef spirit:addressSpaceRef= "io_reg" />        </spirit:master>

    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wait</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_wait</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>io_reg_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>




 <spirit:busInterface><spirit:name>ext_mem</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>

  <spirit:master> <spirit:addressSpaceRef spirit:addressSpaceRef= "ext_mem" />        </spirit:master>


    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>13</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wait</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_wait</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>ext_mem_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>






 <spirit:busInterface><spirit:name>prog_rom_mem</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>


  <spirit:master/>
    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>11</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>prog_rom_mem_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





 <spirit:busInterface><spirit:name>sh_prog_rom_mem</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master/>
    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>11</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_cs</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>


      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>sh_prog_rom_mem_wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>




</spirit:busInterfaces>



<spirit:componentGenerators>


<spirit:componentGenerator>
  <spirit:name>elab_verilog</spirit:name>
  <spirit:phase>102.1</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>configuration</spirit:name>
      <spirit:value>default</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>io_ports</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>



<spirit:componentGenerator>
  <spirit:name>gen_verilog</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>top</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>../verilog</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>


</spirit:componentGenerators>





  <spirit:fileSets>

    <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.body</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>

    </spirit:fileSet>


    <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/top</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


    </spirit:fileSet>


    <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/top</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


    </spirit:fileSet>







  </spirit:fileSets>




<spirit:model>

      <spirit:views>


              <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>






              <spirit:view>
              <spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-common</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>



      </spirit:views>








</spirit:model>







<spirit:memoryMaps>


 <spirit:memoryMap>
  <spirit:name>cpu</spirit:name>

   <spirit:subspaceMap spirit:masterRef="io_reg">
     <spirit:name>io_reg</spirit:name>
     <spirit:baseAddress>0x8000</spirit:baseAddress>
   </spirit:subspaceMap>


   <spirit:subspaceMap spirit:masterRef="data">
     <spirit:name>data</spirit:name>
     <spirit:baseAddress>0x1000</spirit:baseAddress>
   </spirit:subspaceMap>

   <spirit:subspaceMap spirit:masterRef="ext_mem">
     <spirit:name>ext_mem</spirit:name>
     <spirit:baseAddress>0x4000</spirit:baseAddress>
   </spirit:subspaceMap>


   <spirit:subspaceMap spirit:masterRef="prog_rom_mem">
     <spirit:name>prog_rom_mem</spirit:name>
     <spirit:baseAddress>0xc000</spirit:baseAddress>
   </spirit:subspaceMap>


   <spirit:subspaceMap spirit:masterRef="sh_prog_rom_mem">
     <spirit:name>sh_prog_rom_mem</spirit:name>
     <spirit:baseAddress>0xf000</spirit:baseAddress>
   </spirit:subspaceMap>


 </spirit:memoryMap>

</spirit:memoryMaps>





<spirit:addressSpaces>

  <spirit:addressSpace>
    <spirit:name>io_reg</spirit:name>
    <spirit:range>0x8000</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>


  <spirit:addressSpace>
    <spirit:name>data</spirit:name>
    <spirit:range>0x1000</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>



  <spirit:addressSpace>
    <spirit:name>mem</spirit:name>
    <spirit:range>0x0000</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>




  <spirit:addressSpace>
    <spirit:name>ext_mem</spirit:name>
    <spirit:range>0x4000</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>


  <spirit:addressSpace>
    <spirit:name>prog_rom_mem</spirit:name>
    <spirit:range>0xff00</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>


  <spirit:addressSpace>
    <spirit:name>sh_prog_rom_mem</spirit:name>
    <spirit:range>0xc000</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>



</spirit:addressSpaces>






</spirit:component>

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.