OpenCores
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Rev 133

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<?xml version="1.0" encoding="utf-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>logic</spirit:library>
<spirit:name>micro_bus</spirit:name>
<spirit:version>exp5</spirit:version>  <spirit:configuration>default</spirit:configuration>  



<spirit:busInterfaces>

<spirit:busInterface><spirit:name>mb_out</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:slave>
  <spirit:memoryMapRef spirit:memoryMapRef="mb_out"/>
  <spirit:bridge spirit:masterRef="mas_0" spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="mas_1" spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="mas_2" spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="mas_3" spirit:opaque="true"/>
  <spirit:bridge spirit:masterRef="mas_4" spirit:opaque="true"/>
  </spirit:slave>


    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>addr_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rd_in</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wr_in</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>cs_in</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wait</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wait_out</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





<spirit:busInterface><spirit:name>mas_0</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="mas_0"/></spirit:master>

    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_addr_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_rdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_wdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_rd_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_wr_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_0_cs_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>







<spirit:busInterface><spirit:name>mas_1</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="mas_1"/></spirit:master>

    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_addr_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_rdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_wdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_rd_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_wr_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_1_cs_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>








<spirit:busInterface><spirit:name>mas_2</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="mas_2"/></spirit:master>

 
    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_addr_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_rdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_wdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_rd_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_wr_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_2_cs_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





<spirit:busInterface><spirit:name>mas_3</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="mas_3"/></spirit:master> 

    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_addr_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_rdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_wdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_rd_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_wr_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_3_cs_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





<spirit:busInterface><spirit:name>mas_4</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>

  <spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="mas_4"/></spirit:master>


    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_addr_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>3</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_rdata_in</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_wdata_out</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_rd_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_wr_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name>
        </spirit:logicalPort>
        <spirit:physicalPort><spirit:name>mas_4_cs_out</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>





</spirit:busInterfaces>



<spirit:componentGenerators>



<spirit:componentGenerator>
  <spirit:name>elab_verilog</spirit:name>
  <spirit:phase>102.1</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>configuration</spirit:name>
      <spirit:value>exp_default</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>io_ports</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>


<spirit:componentGenerator>
  <spirit:name>gen_verilog</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>top.exp5</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>../verilog</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>



</spirit:componentGenerators>


  <spirit:fileSets>

    <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.body.exp5</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>

    </spirit:fileSet>

    <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/top.exp5</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


    </spirit:fileSet>




    <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/top.exp5</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>



    </spirit:fileSet>






  </spirit:fileSets>




<spirit:model>

      <spirit:views>



              <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>





              <spirit:view>
              <spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-common</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>


      </spirit:views>




<spirit:ports>

<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>



<spirit:port><spirit:name>enable</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

</spirit:ports>


</spirit:model>




<spirit:memoryMaps>


   <spirit:memoryMap>

   <spirit:addressUnitBits>4</spirit:addressUnitBits>
   <spirit:name>mb_out</spirit:name>


  <spirit:subspaceMap spirit:masterRef="mas_0">
     <spirit:name>mas_0</spirit:name>
     <spirit:baseAddress>0x00</spirit:baseAddress>
   </spirit:subspaceMap>


  <spirit:subspaceMap spirit:masterRef="mas_1">
     <spirit:name>mas_1</spirit:name>
     <spirit:baseAddress>0x10</spirit:baseAddress>
   </spirit:subspaceMap>


  <spirit:subspaceMap spirit:masterRef="mas_2">
     <spirit:name>mas_2</spirit:name>
     <spirit:baseAddress>0x20</spirit:baseAddress>
   </spirit:subspaceMap>


  <spirit:subspaceMap spirit:masterRef="mas_3">
     <spirit:name>mas_3</spirit:name>
     <spirit:baseAddress>0x30</spirit:baseAddress>
   </spirit:subspaceMap>

  <spirit:subspaceMap spirit:masterRef="mas_4">
     <spirit:name>mas_4</spirit:name>
     <spirit:baseAddress>0x40</spirit:baseAddress>
   </spirit:subspaceMap>





   <spirit:bank>
     <spirit:name>mas_0</spirit:name>
     <spirit:baseAddress>00</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mas_0</spirit:name>
       <spirit:range>16</spirit:range>
       <spirit:width>8</spirit:width>
     </spirit:addressBlock>
   </spirit:bank>

   <spirit:bank>
     <spirit:name>mas_1</spirit:name>
     <spirit:baseAddress>10</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mas_1</spirit:name>
       <spirit:range>16</spirit:range>
       <spirit:width>8</spirit:width>
     </spirit:addressBlock>
   </spirit:bank>


   <spirit:bank>
     <spirit:name>mas_2</spirit:name>
     <spirit:baseAddress>20</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mas_2</spirit:name>
       <spirit:range>16</spirit:range>
       <spirit:width>8</spirit:width>
     </spirit:addressBlock>
   </spirit:bank>




   <spirit:bank>
     <spirit:name>mas_3</spirit:name>
     <spirit:baseAddress>30</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mas_3</spirit:name>
       <spirit:range>16</spirit:range>
       <spirit:width>8</spirit:width>
     </spirit:addressBlock>
   </spirit:bank>


   <spirit:bank>
     <spirit:name>mas_4</spirit:name>
     <spirit:baseAddress>40</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mas_4</spirit:name>
       <spirit:range>16</spirit:range>
       <spirit:width>8</spirit:width>
     </spirit:addressBlock>
   </spirit:bank>






   </spirit:memoryMap>



</spirit:memoryMaps>


<spirit:addressSpaces>

  <spirit:addressSpace>
    <spirit:name>mas_0</spirit:name>
    <spirit:range>0x10</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>

  <spirit:addressSpace>
    <spirit:name>mas_1</spirit:name>
    <spirit:range>0x10</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>

  <spirit:addressSpace>
    <spirit:name>mas_2</spirit:name>
    <spirit:range>0x10</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>

  <spirit:addressSpace>
    <spirit:name>mas_3</spirit:name>
    <spirit:range>0x10</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>

  <spirit:addressSpace>
    <spirit:name>mas_4</spirit:name>
    <spirit:range>0x10</spirit:range>
    <spirit:width>8</spirit:width>
  </spirit:addressSpace>


</spirit:addressSpaces>




</spirit:component>

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