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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [icarus/] [default/] [wave.sav] - Rev 134

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[timestart] 0
[size] 1920 1176
[pos] 80 0
*-11.000000 7220 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TB.
[treeopen] TB.test.
[treeopen] TB.test.dut.
[treeopen] TB.test.dut.tim_0.
@28
TB.test.clk
TB.test.reset
TB.test.enable
@22
TB.test.reg_mb_addr[15:0]
@28
TB.test.reg_mb_cs
TB.test.reg_mb_wr
@22
TB.test.reg_mb_wdata[7:0]
@28
TB.test.reg_mb_rd
@22
TB.test.reg_mb_rdata[15:0]
TB.test.gpio_0_out[7:0]
TB.test.gpio_0_oe[7:0]
TB.test.gpio_0_lat[7:0]
TB.test.gpio_0_in[7:0]
TB.test.gpio_1_out[7:0]
TB.test.gpio_1_oe[7:0]
TB.test.gpio_1_lat[7:0]
TB.test.gpio_1_in[7:0]
TB.test.dut.gpio.gpio_0_out[7:0]
TB.test.dut.gpio.next_gpio_0_out[7:0]
TB.test.dut.tim_0.count_0[7:0]
@28
TB.test.dut.tim_0.state_0[2:0]
@22
TB.test.dut.tim_0.count_1[7:0]
@28
TB.test.dut.tim_0.state_1[2:0]
@29
TB.test.dut.tim_0.irq[1:0]
[pattern_trace] 1
[pattern_trace] 0

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