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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [verilog/] [tb.ext] - Rev 131
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assign enable = 1'b1;
assign reg_mb_cs = 1'b1;
assign STOP = 1'b0;
assign BAD = 1'b0;