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<h1><a name="socgen ip"></a>SOCGEN IP: SERIAL_RCVR<br>
</h1>
<p><br>
</p>
<p>Table of Contents</p>
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<ul>
<li>
<p style="margin-bottom: 0in;"><a href="#geda_project_wiki">SOCGEN
IP: SERIAL_RCVR<br>
</a></p>
<ul>
<li>
<p style="margin-bottom: 0in;"><a href="#description">Description<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#interface">Interface<br>
</a></p>
</li>
<li>
<p><a
href="../../../../../../socgen_cmp/projects/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v">Source
Code</a></p>
</li>
</ul>
</li>
</ul>
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<h1><img style="width: 640px; height: 480px;" alt="" src="png/serial_xmit.png"><br>
</h1>
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<h2><a name="#description"></a><!-- SECTION "" [2-34] -->Description<br>
</h2>
<p>The Uart is a 8 bit serial port interface transmit engine. Data
Rate is set by a parameter that scales the clk down to a 16 X clock
enable. Parity is also selected with a parameter and if enabled
may be even,odd, always 1 or always 0. <br>
</p>
<p><br>
</p>
<p><br>
</p>
<h2><a name="#interface"></a><!-- SECTION "Why do another 6502?" [35-1160] -->Interface<br>
</h2>
<p>The<br>
</p>
<ul>
<li>
<p style="margin-bottom: 0in;">clk<br>
</p>
</li>
<li>reset</li>
<li>txd_parity</li>
<li>txd_force_parity</li>
<li>txd_data_in[7:0]</li>
<li>txd_load</li>
<li>txd_buffer_empty</li>
<li>txd_pad_out</li>
</ul>
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