URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [verilog/] [top.body] - Rev 131
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always@(posedge clk)
if(reset) rxd_pad_sig <= 1'b1;
else rxd_pad_sig <= pad_in;
always@(posedge clk)
if(reset) start_detect <= 1'b0;
else
if(start_detect)
begin
if(stop_cnt && edge_enable ) start_detect <= !(rxd_pad_sig ^ START_VALUE);
else
if(last_cnt) start_detect <= 1'b0;
else start_detect <= 1'b1;
end
else
if(!(rxd_pad_sig ^ START_VALUE) ) start_detect <= 1'b1;
else start_detect <= start_detect;
always@(posedge clk)
if(reset)
begin
frame_rdy <= 1'b0;
rdy_del <= 2'b00;
end
else
begin
frame_rdy <= rdy_del[1] ;
rdy_del <= {rdy_del[0],last_cnt};
end
always@(posedge clk)
if (reset) frame_avail <= 1'b0;
else
if(frame_rdy) frame_avail <= 1'b1;
else
if(rcv_stb) frame_avail <= 1'b0;
else frame_avail <= frame_avail;
always@(posedge clk)
if(reset)
begin
shift_buffer <= 8'h00;
parity_calc <= 1'b0;
parity_samp <= 1'b0;
frame_parity_error <= 1'b0;
frame_error <= 1'b0;
end
else
if(last_cnt )
begin
shift_buffer <= next_shift_buffer;
parity_calc <= next_parity_calc;
parity_samp <= next_parity_samp;
frame_parity_error <= (next_parity_samp ^ next_parity_calc) && parity_enable;
frame_error <= next_frame_error;
end
else
begin
shift_buffer <= shift_buffer;
parity_calc <= parity_calc;
parity_samp <= parity_samp;
frame_parity_error <= frame_parity_error;
frame_error <= frame_error;
end
assign divider_reset = reset || (!start_detect);