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assign  txd_break_n  = !txd_break ;


   
always@(posedge clk)
  if(reset)            rts_pad_out  <= 1'b0;
  else                 rts_pad_out  <= rts_in;

always@(posedge clk)
  if(reset)            cts_out      <= 1'b0;
  else                 cts_out      <= cts_pad_in;

   



generate

if(DIV == 0)
  begin   
assign    baud_clk_div = baud_clk;
  end
else   
begin
cde_divider_def
#(.SIZE(DIV_SIZE))  
baud_divider  (
         .clk             ( clk          ),
         .reset           ( reset        ),
         .divider_in      ( divider_in   ),
         .enable          ( baud_clk     ),
         .divider_out     ( baud_clk_div )
         );
end  

endgenerate






     always@(*)  xmit_start       = txd_load;
     assign fifo_data_out    = txd_data_in;
     assign txd_buffer_empty = cde_buffer_empty;