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assign  txd_break_n  = !txd_break ;

   
   
always@(posedge clk)
  if(reset)            rts_pad_out  <= 1'b0;
  else                 rts_pad_out  <= rts_in;

always@(posedge clk)
  if(reset)            cts_out      <= 1'b0;
  else                 cts_out      <= cts_pad_in;

   



   
reg  [DIV_SIZE-1:0]        baud_divide_cnt;
reg                        baud_divider_out;

always@(posedge clk)
  if(reset)            baud_divider_out    <= 1'b1;
  else
  if(!baud_clk)        baud_divider_out    <= 1'b0;  
  else                 baud_divider_out    <=  ( baud_divide_cnt == {DIV_SIZE{1'b0}} );       



always@(posedge clk)
  if(reset)                 baud_divide_cnt    <= divider_in;
  else
  if(!baud_clk)             baud_divide_cnt    <= baud_divide_cnt;
  else
  if(!(|baud_divide_cnt))   baud_divide_cnt    <= divider_in;
  else                      baud_divide_cnt    <= baud_divide_cnt - 'b1;




generate

if(DIV == 0)
  begin   
assign    baud_clk_div = baud_clk;
  end
else   
begin

assign    baud_clk_div  = baud_divider_out;
end  

endgenerate





   

always@(posedge clk)
  if(reset)
    begin
       xmit_start     <= 1'b0;
    end
  else
  if( !fifo_empty &&   cde_buffer_empty &&  !xmit_start )  
    begin
       xmit_start     <= 1'b1;
    end
  else
    begin
       xmit_start     <= 1'b0;
    end

assign txd_buffer_empty =      !fifo_full;

assign fifo_pop =  !fifo_empty &&   cde_buffer_empty && ! xmit_start;