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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [char_display] - Rev 134
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module `VARIANT`CHAR_DISPLAY
#(parameter H_ACTIVE=0
)
(
input wire clk,
input wire reset,
input wire [2:0] subchar_line, // the line number within a character block 0-8
input wire [2:0] subchar_pixel, // the pixel number within a character block 0-8
input wire [7:0] ascii_code,
output wire pixel_on,
input wire [13:0] char_read_addr,
input wire [13:0] char_write_addr,
input wire [7:0] char_write_data,
input wire [7:0] char_gen_rom_data,
input wire char_write_enable
);
// the character generator block includes the character RAM
// and the character generator ROM
`VARIANT`CHAR_GEN
CHAR_GEN
(
.clk ( clk ),
.reset ( reset ), // reset signal
.char_write_addr ( char_write_addr ), // write address
.char_write_data ( char_write_data ), // write data
.char_write_enable ( char_write_enable ), // write enable
.char_read_addr ( char_read_addr ), // read address of current character
.subchar_line ( subchar_line ), // current line of pixels within current character
.subchar_pixel ( subchar_pixel ), // current column of pixels withing current character
.char_gen_rom_data ( char_gen_rom_data ),
.pixel_on ( pixel_on ),
.ascii_code ( ascii_code )
);
endmodule //CHAR_DISPLAY