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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [char_gen] - Rev 134
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module `VARIANT`CHAR_GEN
(
input wire clk,
input wire reset,
input wire [13:0] char_write_addr,
input wire [7:0] char_write_data,
input wire char_write_enable,
input wire [13:0] char_read_addr, // character address "0" is upper left character
input wire [2:0] subchar_line, // line number within 8 line block
input wire [2:0] subchar_pixel, // pixel position within 8 pixel block
input wire [7:0] ascii_code,
input wire [7:0] char_gen_rom_data,
output reg pixel_on
);
reg latch_data;
reg latch_low_data;
reg shift_high;
reg shift_low;
reg [3:0] latched_low_char_data;
reg [7:0] latched_char_data;
// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM
always @ (posedge clk )begin
if (reset) begin
latch_data <= 1'b0;
end
else if (subchar_pixel == 3'b110) begin
latch_data <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
latch_data <= 1'b0;
end
end
always @ (posedge clk )begin
if (reset) begin
latch_low_data <= 1'b0;
end
else if (subchar_pixel == 3'b010) begin
latch_low_data <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
latch_low_data <= 1'b0;
end
end
always @ (posedge clk )begin
if (reset) begin
shift_high <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
shift_high <= 1'b0;
end
else if (subchar_pixel == 3'b111) begin
shift_high <= 1'b1;
end
end
always @ (posedge clk )begin
if (reset) begin
shift_low <= 1'b0;
end
else if (subchar_pixel == 3'b011) begin
shift_low <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
shift_low <= 1'b0;
end
end
// serialize the CHARACTER MODE data
always @ (posedge clk ) begin
if (reset)
begin
pixel_on <= 1'b0;
latched_low_char_data <= 4'h0;
latched_char_data <= 8'h00;
end
else if (shift_high)
begin
pixel_on <= latched_char_data [7];
latched_char_data [7] <= latched_char_data [6];
latched_char_data [6] <= latched_char_data [5];
latched_char_data [5] <= latched_char_data [4];
latched_char_data [4] <= latched_char_data [7];
if(latch_low_data) begin
latched_low_char_data [3:0] <= latched_char_data [3:0];
end
else begin
latched_low_char_data [3:0] <= latched_low_char_data [3:0];
end
end
else if (shift_low)
begin
pixel_on <= latched_low_char_data [3];
latched_low_char_data [3] <= latched_low_char_data [2];
latched_low_char_data [2] <= latched_low_char_data [1];
latched_low_char_data [1] <= latched_low_char_data [0];
latched_low_char_data [0] <= latched_low_char_data [3];
if (latch_data) latched_char_data [7:0] <= char_gen_rom_data[7:0];
else latched_char_data [7:0] <= latched_char_data [7:0];
end
else
begin
latched_low_char_data [3:0] <= latched_low_char_data [3:0];
latched_char_data [7:0] <= latched_char_data [7:0];
pixel_on <= pixel_on;
end
end
endmodule //CHAR_GEN