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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [Heda/] [absDef/] [wb_b.4_rtl.txt] - Rev 131

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opencores.org:wishbone:wb:b.4_rtl
        --------------------------------------------------------------------------------------------------------
        Filename:  ./projects/opencores.org/wishbone/busDefs/abstractors/wb_b.4_rtl.xml
        VLNV-ad     opencores.org_wishbone_wb_b.4_rtl
        VLNV-bt     opencores.org_wishbone_wb_b.4
             SystemGroup Name CLOCK 
             SystemGroup Name RESET 
             SystemGroup Name ENABLE 

Port:  clk   CLOCK  Requires Driver  clock    
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Port:  enable       
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Port:  rst   RESET  Requires Driver  singleShot    
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Port:  adr       
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Port:  cyc       
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Port:  wdata       
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Port:  rdata       
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Port:  ack       
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Port:  err       
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Port:  rty       
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Port:  stall       
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Port:  sel       
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Port:  stb       
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Port:  wtgd       
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Port:  we       
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