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// Internal signals
reg [dwidth -1:0] q;
always@(posedge clk)
if(reset)
begin
adr <= {awidth{1'b0}};
dout <= {dwidth{1'b0}};
cyc <= 1'b0;
stb <= 1'b0;
we <= 1'h0;
sel <= {dwidth/8{1'b0}};
end