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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_master_model                                             ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  Based on:                                                   ////
////      - i2c/bench/verilog/wb_master_model.v                   ////
////        Copyright (C) 2001 Richard Herveille                  ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module model_master
#( parameter dwidth = 32,
   parameter awidth = 32
 )(
  input wire                  clk, 
  input wire                  reset,
  output reg [awidth   -1:0]  adr,
  output reg [dwidth   -1:0]  dout,
  output reg                  cyc, 
  output reg                  stb,
  output reg                  we,
  output reg [dwidth/8 -1:0]  sel,
  input  wire [dwidth   -1:0] din,
  input  wire                 ack, 
  input  wire                 err, 
  input  wire                 rty
);
 
  // Internal signals
  reg    [dwidth   -1:0] q;
always@(posedge clk)
  if(reset)
    begin
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b0;
      stb  <= 1'b0;
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
    end
 
 
 
endmodule