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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [syn/] [model_monitor.v] - Rev 131
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's simulation monitor //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// wishbone protocal monitor //// //// //// //// To Do: //// //// //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// module model_monitor #(parameter TEST_NAME="unspecified", parameter INSTANCE="none", parameter ADD_WIDTH=32, parameter DATA_WIDTH=32 ) ( input wire clk, input wire reset, input wire [ADD_WIDTH-1:0] wb_adr, input wire wb_ack, input wire wb_err, input wire wb_cyc, input wire wb_stb, input wire wb_we, input wire [DATA_WIDTH-1:0] wb_read, input wire [DATA_WIDTH-1:0] wb_write, input wire [3:0] wb_sel ); endmodule