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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.design.xml] - Rev 135

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<ipxact:design 
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>wishbone</ipxact:library>
<ipxact:name>wb_memory</ipxact:name>
<ipxact:version>def.design</ipxact:version>  





<ipxact:adHocConnections>

    <ipxact:adHocConnection>
      <ipxact:name>clk_i</ipxact:name>
      <ipxact:externalPortReference portRef="slave_clk_clk"/>
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="clk"/>
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="clk"/>
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="clk"/>
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="clk"/>
    </ipxact:adHocConnection>



   <ipxact:adHocConnection>
      <ipxact:name>sel_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_sel"  left="0" right="0" />
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="be"/>
    </ipxact:adHocConnection>

   <ipxact:adHocConnection>
      <ipxact:name>sel_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_sel" left="1" right="1" />
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="be"/>
    </ipxact:adHocConnection>

   <ipxact:adHocConnection>
      <ipxact:name>sel_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_sel" left="2" right="2" />
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="be"/>
    </ipxact:adHocConnection>

   <ipxact:adHocConnection>
      <ipxact:name>sel_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_sel" left="3" right="3" />
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="be"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>dat_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_wdata" left="7" right="0" />
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="wdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_wdata" left="15" right="8" />
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="wdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_wdata" left="23" right="16" />
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="wdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_wdata" left="31" right="24" />
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="wdata"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>dat_o</ipxact:name>
      <ipxact:externalPortReference portRef="wb_rdata" left="7" right="0" />
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="rdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_o</ipxact:name>
      <ipxact:externalPortReference portRef="wb_rdata" left="15" right="8" />
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="rdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_o</ipxact:name>
      <ipxact:externalPortReference portRef="wb_rdata" left="23" right="16" />
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="rdata"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>dat_o</ipxact:name>
      <ipxact:externalPortReference portRef="wb_rdata" left="31" right="24" />
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="rdata"/>
    </ipxact:adHocConnection>




    <ipxact:adHocConnection>
      <ipxact:name>adr_i</ipxact:name>
      <ipxact:externalPortReference portRef="wb_adr" left="adr_width+1" right="2" />
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="addr"/>
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="addr"/>
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="addr"/>
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="addr"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>sram_wr</ipxact:name>
      <ipxact:externalPortReference portRef="sram_wr"/>
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="wr"/>
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="wr"/>
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="wr"/>
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="wr"/>
    </ipxact:adHocConnection>


   <ipxact:adHocConnection  tiedValue="1'b1"  >
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="rd"/>
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="rd"/>
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="rd"/>
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="rd"/>
      <ipxact:internalPortReference componentRef="rambyte_0" portRef="cs"/>
      <ipxact:internalPortReference componentRef="rambyte_1" portRef="cs"/>
      <ipxact:internalPortReference componentRef="rambyte_2" portRef="cs"/>
      <ipxact:internalPortReference componentRef="rambyte_3" portRef="cs"/>
    </ipxact:adHocConnection>


</ipxact:adHocConnections>






<ipxact:componentInstances>



<ipxact:componentInstance>
<ipxact:instanceName>rambyte_0</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="byte" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="ADDR">adr_width</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">mem_size</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">0</ipxact:configurableElementValue>

</ipxact:configurableElementValues>
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>rambyte_1</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="byte" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="ADDR">adr_width</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">mem_size</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">0</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>


<ipxact:componentInstance>
<ipxact:instanceName>rambyte_2</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="byte" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="ADDR">adr_width</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">mem_size</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">0</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>


<ipxact:componentInstance>
<ipxact:instanceName>rambyte_3</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="sram" version="byte" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="ADDR">adr_width</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WORDS">mem_size</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="WRITETHRU">0</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>

</ipxact:componentInstances>





</ipxact:design>

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