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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Rev 134

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>wishbone</spirit:library>
<spirit:name>wb_memory</spirit:name>
<spirit:version>def</spirit:version>  <spirit:configuration>default</spirit:configuration>  



<spirit:busInterfaces>


 <spirit:busInterface><spirit:name>slave_clk</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>clk_i</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>slave_reset</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>reset</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rst_i</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


<spirit:busInterface><spirit:name>wb</spirit:name>
   <spirit:busType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="def"/>
   <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wishbone" spirit:version="rtl"/>
   <spirit:slave><spirit:memoryMapRef spirit:memoryMapRef="wb"/>  </spirit:slave>
     <spirit:portMaps>

        <spirit:portMap>
         <spirit:logicalPort><spirit:name>adr</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>adr_i</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>wb_addr_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>



        <spirit:portMap>
         <spirit:logicalPort><spirit:name>wdata</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>dat_i</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>rdata</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>dat_o</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>wb_data_width-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>sel</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>sel_i</spirit:name>
           <spirit:wire><spirit:vector><spirit:left>wb_byte_lanes-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>we</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>we_i</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>cyc</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>cyc_i</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>stb</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>stb_i</spirit:name>
         </spirit:physicalPort>
       </spirit:portMap>


        <spirit:portMap>
         <spirit:logicalPort><spirit:name>ack</spirit:name>
         </spirit:logicalPort>
         <spirit:physicalPort><spirit:name>ack_o</spirit:name>
         <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
         </spirit:physicalPort>
       </spirit:portMap>


     </spirit:portMaps>

</spirit:busInterface>

</spirit:busInterfaces>






<spirit:componentGenerators>




<spirit:componentGenerator>
  <spirit:name>gen_verilog</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>  
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>wb_memory_def</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>





</spirit:componentGenerators>








<spirit:model>
       <spirit:views>



              <spirit:view>
              <spirit:name>Hierarchical</spirit:name>
              
              <spirit:hierarchyRef spirit:vendor="opencores.org" 
                                   spirit:library="wishbone" 
                                   spirit:name="wb_memory" 
                                   spirit:version="def.design"/>
              </spirit:view>

              <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>






              <spirit:view>
              <spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-common</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>



              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>

      </spirit:views>




<spirit:modelParameters>
   <spirit:modelParameter><spirit:name>wb_addr_width</spirit:name><spirit:value>24</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>wb_data_width</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>wb_byte_lanes</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>dat_width</spirit:name><spirit:value>32</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>adr_width</spirit:name><spirit:value>14</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>mem_size</spirit:name><spirit:value>16384</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>SRAM_MEM_0_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>SRAM_MEM_1_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>SRAM_MEM_2_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
   <spirit:modelParameter><spirit:name>SRAM_MEM_3_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>

</spirit:modelParameters>



</spirit:model>





  <spirit:fileSets>


    <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.body</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>


    </spirit:fileSet>


    <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/wb_memory_def</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/sim/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>







    </spirit:fileSet>



    <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/wb_memory_def</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/syn/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>




    </spirit:fileSet>




  </spirit:fileSets>





</spirit:component>

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