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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [icarus/] [default/] [test_define] - Rev 131

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reg [31:0] d;


initial
 begin
 $display("              ");
 $display("          ===================================================");
 $display("%t  Test Start",$realtime  );
 $display("          ===================================================");
 $display("              ");
 test.cg.next(8);
 
 test.cg.next(88);
 $display("%t  Out of reset  ",$realtime  );

 test.i_wb_master.wb_write( 20'h00000,4'b0001, 32'h00000012); 
 test.i_wb_master.wb_write( 20'h00000,4'b0010, 32'h00003400); 
 test.i_wb_master.wb_write( 20'h00000,4'b0100, 32'h00560000);  
 test.i_wb_master.wb_write( 20'h00000,4'b1000, 32'h78000000); 


 test.cg.next(8);
 test.i_wb_master.wb_write( 20'h00040,4'b1111, 32'h5a);   
 test.cg.next(8);
 test.i_wb_master.wb_write( 20'h00080,4'b1111, 32'h208);  
 test.cg.next(8);
 test.i_wb_master.wb_write( 20'h000c0,4'b1111, 32'h01);     



 test.i_wb_master.wb_read( 20'h00000, d);  
 test.cg.next(8);
 test.i_wb_master.wb_read( 20'h00040, d);    
 test.cg.next(8);
 test.i_wb_master.wb_read( 20'h00080, d);   
 test.cg.next(8);
 test.i_wb_master.wb_read( 20'h000c0, d);      
 test.cg.next(8);

 $display("%t verified registers", $realtime);
 test.i_wb_master.wb_cmp( 20'h00000,4'b1111, 32'h78563412 );  
 test.cg.next(8);
 test.i_wb_master.wb_cmp( 20'h00040,4'b1111, 32'h5a );    
 test.cg.next(8);
 test.i_wb_master.wb_cmp( 20'h00080,4'b1111, 32'h208 );   
 test.cg.next(8);
 test.i_wb_master.wb_cmp( 20'h000c0,4'b1111, 32'h01 );      
 test.cg.next(8);

 test.cg.next(100);



test.cg.exit;
end









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