URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [bus16_lit_default/] [wave.sav] - Rev 133
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[timestart] 0
[size] 1613 999
[pos] 785 13
*-12.000000 6740 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TB.
[treeopen] TB.test.
[treeopen] TB.test.dut.
[treeopen] TB.test.dut.regs.
@28
TB.test.cts_pad_i
TB.test.dcd_pad_i
TB.test.dsr_pad_i
TB.test.ri_pad_i
TB.test.dtr_pad_o
TB.test.int_o
TB.test.reset
TB.test.rts_pad_o
TB.test.srx_pad_i
TB.test.stx_pad_o
TB.test.wb_ack_o
TB.test.wb_cyc_i
@22
TB.test.wb_sel_i[3:0]
@28
TB.test.wb_stb_i
TB.test.wb_we_i
@22
TB.test.dut.wb_adr_i[7:0]
@28
TB.test.dut.wb_cyc_i
@22
TB.test.dut.micro_reg.fc_reg[7:0]
TB.test.dut.micro_reg.ie_dlh_reg[7:0]
TB.test.dut.micro_reg.rb_dll_reg[7:0]
TB.test.dut.micro_reg.ii_reg[3:0]
TB.test.dut.micro_reg.lc_reg[7:0]
TB.test.dut.micro_reg.ls_reg[7:0]
TB.test.dut.micro_reg.mc_reg[4:0]
TB.test.dut.regs.ier[3:0]
@28
TB.test.dut.micro_reg.lc_reg_dec
TB.test.dut.micro_reg.lc_reg_wr
@22
TB.test.dut.micro_reg.lc_reg[7:0]
TB.test.dut.micro_reg.next_lc_reg[7:0]
TB.test.dut.micro_reg.addr[7:0]
TB.test.dut.micro_reg.wdata[15:0]
@23
TB.test.dut.regs.dl[15:0]
[pattern_trace] 1
[pattern_trace] 0
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