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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [default/] [test_define] - Rev 131

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`include  "../../testbenches/elab/wb_uart16550_def_tb/sw/wb.v" 


reg [31:0] d;



initial
 begin
 $display("              ");
 $display("          ===================================================");
 $display("%t  Test Start",$realtime  );
 $display("          ===================================================");
 $display("              ");
 test.cg.next(1);
 test.cts_pad_R  <= 1'b0;
 test.dcd_pad_R  <= 1'b0;
 test.dsr_pad_R  <= 1'b0;
 test.ri_pad_R   <= 1'b0;
 test.cg.next(8);
 
 $display("%t    out of reset  ",$realtime  );
 test.cg.next(88);

fork
begin
          test.i_wb_master.wb_write(fc_reg,1'b1,8'hc7 ); 
          test.cg.next(20);
          test.i_wb_master.wb_write(ie_reg,1'b1,8'h00 );
          test.cg.next(20);
          test.i_wb_master.wb_write(lc_reg,1'b1,8'h03 );
          test.cg.next(20);
          test.i_wb_master.wb_write(lc_reg,1'b1,8'h83 );
          test.cg.next(20);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h0d );
          test.cg.next(20);
          test.i_wb_master.wb_write(ie_reg,1'b1,8'h00 );
          test.cg.next(20);
          test.i_wb_master.wb_write(lc_reg,1'b1,8'h03 );
          test.cg.next(20);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h48 );
          test.i_wb_master.wb_read(ls_reg,d );
          test.cg.next(10000);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h65 );
          test.cg.next(10000);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6c );
          test.cg.next(10000);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6c );
          test.cg.next(10000);
          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6f );
          test.cg.next(50000);
          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h34 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(ie_reg,1'b1,8'h00 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(ii_reg,1'b1,8'hc1 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(lc_reg,1'b1,8'h03 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(mc_reg,1'b1,8'h00 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(ls_reg,1'b1,8'h61 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(ms_reg,1'b1,8'h00 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(sr_reg,1'b1,8'h00 );
          test.cg.next(100);
          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h43 );
          test.cg.next(100);
          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h56 );
          test.cg.next(500);
          test.i_wb_master.wb_cmp(debug_0_reg,1'b1,8'h60 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(debug_0_reg+1,1'b1,8'h10 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(debug_0_reg+2,1'b1,8'h03 );
          test.cg.next(50);
          test.i_wb_master.wb_cmp(debug_0_reg+3,1'b1,8'h00 );
          test.cg.next(500);



end








 begin
 test.uart_model.rx_parity_enable  = 1'b0;
 test.uart_model.txd_parity_enable = 1'b0;
 test.uart_model.rx_parity         = 1'b1;
 test.uart_model.txd_parity        = 1'b1;
 test.cg.next(10);
 test.uart_model.rcv_byte(8'h48);
 test.uart_model.send_byte(8'h34);
 test.cg.next(10);
 test.uart_model.rcv_byte(8'h65);
 test.cg.next(10);
 test.uart_model.rcv_byte(8'h6c);
 test.cg.next(10);
 test.uart_model.rcv_byte(8'h6c);
 test.cg.next(10);
 test.uart_model.rcv_byte(8'h6f);
 test.cg.next(10);
 test.uart_model.send_byte(8'h43);
 test.cg.next(10);
 test.uart_model.send_byte(8'h56);
 end
 join
 test.cg.exit;
end









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