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reg  cts_pad_R;
reg  dcd_pad_R;
reg  dsr_pad_R;
reg  ri_pad_R;


assign   cts_pad_i   = cts_pad_R;
assign   dcd_pad_i   = dcd_pad_R;
assign   dsr_pad_i   = dsr_pad_R;
assign   ri_pad_i    = ri_pad_R;

assign wb_clk_i = clk;
assign wb_rst_i = reset;

assign STOP = 1'b0;
assign BAD = 1'b0;