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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [sim/] [testbenches/] [verilog/] [tb.ext] - Rev 135
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assign A_CLK = clk;pullup pu_jtag ( JTAG_TDO );reg [1:0] SW_reg;reg [1:0] BTN_reg;initialbeginSW_reg = 2'b00;BTN_reg = 2'b00;endassign SW = SW_reg;assign BTN = BTN_reg;assign STOP = 1'b0;assign BAD = 1'b0;