Subversion Repositories socgen

v 20031231 1
L 300 800 600 800 3 0 0 0 -1 -1
L 300 200 600 200 3 0 0 0 -1 -1
A 40 500 400 312 97 3 0 0 0 -1 -1
A 600 600 400 270 76 3 0 0 0 -1 -1
A 600 400 400 14 76 3 0 0 0 -1 -1
L 300 800 300 1000 3 0 0 0 -1 -1
L 300 200 300 0 3 0 0 0 -1 -1
V 1050 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 1100 500 1300 500 1 0 1
{
T 1000 500 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 500 5 8 0 0 0 0 1
pinseq=1
}
V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 200 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 200 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 200 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
V 250 700 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 200 700 0 700 1 0 1
{
T 300 700 5 8 0 0 0 0 1
pinnumber=IN3
T 300 700 5 8 0 0 0 0 1
pinseq=5
}
V 250 900 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 200 900 0 900 1 0 1
{
T 300 900 5 8 0 0 0 0 1
pinnumber=IN4
T 300 900 5 8 0 0 0 0 1
pinseq=6
}
T 400 100 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=and
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL