Subversion Repositories socgen

v 20031231 1
L 300 1100 600 1100 3 0 0 0 -1 -1
L 300 500 600 500 3 0 0 0 -1 -1
A 40 800 400 312 97 3 0 0 0 -1 -1
A 600 900 400 270 76 3 0 0 0 -1 -1
A 600 700 400 14 76 3 0 0 0 -1 -1
L 300 1100 300 1600 3 0 0 0 -1 -1
L 300 500 300 0 3 0 0 0 -1 -1
P 1000 800 1300 800 1 0 1
{
T 1000 800 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 800 5 8 0 0 0 0 1
pinseq=1
}
P 300 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
P 300 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
P 300 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
P 300 700 0 700 1 0 1
{
T 300 700 5 8 0 0 0 0 1
pinnumber=IN3
T 300 700 5 8 0 0 0 0 1
pinseq=5
}
P 300 900 0 900 1 0 1
{
T 300 900 5 8 0 0 0 0 1
pinnumber=IN4
T 300 900 5 8 0 0 0 0 1
pinseq=6
}
P 300 1100 0 1100 1 0 1
{
T 300 1100 5 8 0 0 0 0 1
pinnumber=IN5
T 300 1100 5 8 0 0 0 0 1
pinseq=7
}
P 300 1300 0 1300 1 0 1
{
T 300 1300 5 8 0 0 0 0 1
pinnumber=IN6
T 300 1300 5 8 0 0 0 0 1
pinseq=8
}
P 300 1500 0 1500 1 0 1
{
T 300 1500 5 8 0 0 0 0 1
pinnumber=IN7
T 300 1500 5 8 0 0 0 0 1
pinseq=9
}
T 400 400 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=or
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL