Subversion Repositories socgen

v 20031231 1
L 400 1000 600 1000 3 0 0 0 -1 -1
L 400 400 600 400 3 0 0 0 -1 -1
A 40 700 400 312 97 3 0 0 0 -1 -1
A 140 700 400 312 97 3 0 0 0 -1 -1
A 600 800 400 270 76 3 0 0 0 -1 -1
A 600 600 400 14 76 3 0 0 0 -1 -1
L 300 1000 300 1400 3 0 0 0 -1 -1
L 300 400 300 0 3 0 0 0 -1 -1
V 1050 700 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 1100 700 1300 700 1 0 1
{
T 1000 700 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 700 5 8 0 0 0 0 1
pinseq=1
}
P 300 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
P 300 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
P 300 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
P 300 700 0 700 1 0 1
{
T 300 700 5 8 0 0 0 0 1
pinnumber=IN3
T 300 700 5 8 0 0 0 0 1
pinseq=5
}
P 300 900 0 900 1 0 1
{
T 300 900 5 8 0 0 0 0 1
pinnumber=IN4
T 300 900 5 8 0 0 0 0 1
pinseq=6
}
P 300 1100 0 1100 1 0 1
{
T 300 1100 5 8 0 0 0 0 1
pinnumber=IN5
T 300 1100 5 8 0 0 0 0 1
pinseq=7
}
P 300 1300 0 1300 1 0 1
{
T 300 1300 5 8 0 0 0 0 1
pinnumber=IN6
T 300 1300 5 8 0 0 0 0 1
pinseq=8
}
T 400 300 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=xnor
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL