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https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [tasks] - Rev 135
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// Taskstask automatic next;input [31:0] num;repeat (num) @ (posedge clk);endtask // next// idle cycletask u_idle;beginaddr <= 24'h000000;wdata <= 16'h0000;rd <= 1'b0;cs <= 2'b00;wr <= 1'b0;ub <= 1'b0;lb <= 1'b0;mask_rdata <= 16'h0000;next(1);endendtask// write cycletask u_write;input [23:0] a;input [15:0] d;begin$display("%t %m cycle %x %x",$realtime,a,d );addr <= a;wdata <= d;rd <= 1'b0;cs <= 2'b01;wr <= 1'b1;ub <= 1'b1;lb <= 1'b1;next(4);rd <= 1'b0;cs <= 2'b00;wr <= 1'b0;ub <= 1'b0;lb <= 1'b0;next(1);endendtask// read cycletask u_read;input [23:0] a;output [15:0] d;beginaddr <= a;wdata <= 16'h0000;rd <= 1'b1;cs <= 2'b01;wr <= 1'b0;ub <= 1'b1;lb <= 1'b1;next(4);d <= rdata;$display("%t %m cycle %x %x",$realtime,a,rdata );rd <= 1'b1;next(1);rd <= 1'b0;ub <= 1'b0;lb <= 1'b0;cs <= 2'b00;next(1);endendtask// Compare cycle (read data from location and compare with expected data)task u_cmp;input [23:0] a;input [15:0] d_exp;beginaddr <= a;wdata <= 16'h0000;rd <= 1'b1;ub <= 1'b1;lb <= 1'b1;cs <= 2'b01;wr <= 1'b0;exp_rdata <= d_exp;next(5);mask_rdata <= 16'hffff;next(1);$display("%t %m cycle %x %x",$realtime,a,d_exp );mask_rdata <= 16'h0000;rd <= 1'b0;ub <= 1'b0;lb <= 1'b0;cs <= 2'b00;next(1);endendtask
