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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_mem_model/] [rtl/] [verilog/] [logic] - Rev 135
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always@(posedge clk)if(reset)beginio_in_mem_ready <= 1'b0;io_in_mem_valid <= 1'b0;io_mem_backup_en <= 1'b0;io_mem_req_cmd_ready <= 1'b0;io_mem_req_data_ready <= 1'b0;io_mem_resp_bits_data <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;io_mem_resp_bits_tag <= 5'b00000;io_mem_resp_ready <= 1'b0;io_mem_resp_valid <= 1'b0;io_out_mem_ready <= 1'b0;io_out_mem_valid <= 1'b0;end