Subversion Repositories socgen

reg   [WIDTH-1:0]          filtered_value;
reg   [WIDTH:1]            fail;
   
assign         signal = drive_value;
      
always @(posedge clk)   filtered_value <=   signal;
always @(posedge clk)   fail           <=   mask & (signal^ expected_value);  


initial
  begin
    cg.next(3);
    while(1)
      begin
      if(fail !== {WIDTH{1'b0}})        
           begin
           $display("%t %m              value %x   failure on bit(s)  %b",$realtime,filtered_value,fail );
           cg.fail(MESG);
           end
      cg.next(1);
      end // while (1)
  end // initial begin