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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [verilog/] [logic] - Rev 134

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always@(posedge clk)
  if(reset)
    begin
      addr          <=  24'h0000;
      wdata         <=  16'h0000;
      wr            <=  1'b0;
      rd            <=  1'b0;
      cs            <=  2'b00;
      ub            <=  1'b0;
      lb            <=  1'b0;
      exp_rdata     <=  16'h0000;
      mask_rdata    <=  16'h0000;       
   end

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