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module micro_bus16_model_def
#(parameter DELAY    = 15,
  parameter WIDTH    = 10
  )
 
 
 (
  input wire                  clk, 
  input wire                  reset,
  input wire [15:0]           rdata,
 
  output reg [23:0]           addr,
  output reg [15:0]           wdata,
  output reg [1:0]            cs,
  output reg                  rd,
  output reg                  wr,
  output reg                  ub,
  output reg                  lb
 
 
 
);
 
 
   reg [15:0]  exp_rdata;
   reg [15:0]  mask_rdata;
 
 
 
 
io_probe_in 
 #(.MESG         ("micro rdata Error"),
   .WIDTH        (16)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  rdata      )
  );      
 
 
always@(posedge clk)
  if(reset)
    begin
      addr  <=  24'h000000;
      wdata <=  16'h0000;
      wr    <=  1'b0;
      rd    <=  1'b0;
      cs    <=  2'b00;
      ub    <=  1'b0;
      lb    <=  1'b0;
      exp_rdata    <=  16'h0000;
      mask_rdata    <=  16'h0000;       
   end
 
 
 
 
 
 
 
endmodule