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https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [verilog/] [top.sim] - Rev 134
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always@(posedge clk)
if(reset)
begin
addr <= 16'h0000;
wdata <= 8'h00;
wr <= 1'b0;
rd <= 1'b0;
cs <= 1'b1;
exp_rdata <= 8'h00;
mask_rdata <= 8'h00;
end
// Tasks
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
// write cycle
task u_write;
input [addr_width-1:0] a;
input [7:0] d;
begin
$display("%t %m cycle %x %x",$realtime,a,d );
addr <= a;
wdata <= d;
rd <= 1'b0;
wr <= 1'b1;
next(1);
wr <= 1'b0;
next(1);
end
endtask
// read cycle
task u_read;
input [addr_width-1:0] a;
output [7:0] d;
begin
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
next(2);
d <= rdata;
$display("%t %m cycle %x %x",$realtime,a,rdata );
rd <= 1'b1;
next(1);
rd <= 1'b0;
end
endtask
// Compare cycle (read data from location and compare with expected data)
task u_cmp;
input [addr_width-1:0] a;
input [7:0] d_exp;
begin
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
exp_rdata <= d_exp;
next(1);
mask_rdata <= 8'hff;
next(1);
$display("%t %m cycle %x %x",$realtime,a,d_exp );
mask_rdata <= 8'h00;
rd <= 1'b0;
end
endtask
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