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module micro_bus_model_def
#(parameter addr_width   = 16,
  parameter OUT_DELAY    = 15,
  parameter OUT_WIDTH    = 10
  )
 
 
 (
  input wire                  clk, 
  input wire                  reset,
 
  output reg [addr_width-1:0]           addr,
  output reg [7:0]            wdata,
  output reg                  rd,
  output reg                  wr,
  output reg                  cs,
 
  input  wire [7:0]           rdata
);
 
 
   reg [7:0]  exp_rdata;
   reg [7:0]  mask_rdata;
 
always@(posedge clk)
  if(reset)
    begin
      addr          <= 16'h0000;
      wdata         <=  8'h00;
      wr            <=  1'b0;
      rd            <=  1'b0;
      cs            <=  1'b1;
      exp_rdata     <=  8'h00;
      mask_rdata    <=  8'h00;       
   end
 
 
 
io_probe_in 
 #(.MESG         ("micro rdata Error"),
   .WIDTH        (8)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  rdata      )
  );      
 
 
endmodule