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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.syn] - Rev 134
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reg [7:0] memoryl [1<<MEM_BITS-1:0];
reg [7:0] memoryu [1<<MEM_BITS-1:0];
reg [DQ_BITS-1 : 0] dq_out;
// Write Memory
// Read Memory
always@(*) dq_out[7:0] = 8'h0;
always@(*) dq_out[15:8] = 8'h0;
// Tristate output
// assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};