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   reg [31:0]  exp_rdata;
   reg [31:0]  mask_rdata;

      
always@(posedge clk)
  if(reset)
    begin
      dbg_adr_i      <=  32'h00000000;
      dbg_dat_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      dbg_stall_i    <=  1'b1;
      dbg_ewt_i      <=  1'b0;
      exp_rdata      <=  32'h00000000;
      mask_rdata     <=  32'h00000000;       
      end // if (reset)





io_probe_in 
 #(.MESG         ("or1200 rdata Error"),
   .WIDTH        (32)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  dbg_dat_o  )
  );      


  // Tasks


   
task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);       
endtask // next


   

  
  // write cycle
  task u_write;
    input [31:0] a;
    input  [31:0] d;
  
    begin

      $display("%t %m cycle %x %x",$realtime,a,d );
       
      dbg_adr_i      <=  a;
      dbg_dat_i      <=  d;
      dbg_we_i       <=  1'b1;
      dbg_stb_i      <=  1'b1;
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_dat_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;

    end
  endtask
  


// read cycle
  task u_read;
    input   [31:0]  a;
    output  [31:0]   d;
  
     begin
      
      dbg_adr_i      <=  a;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b1;
      next(4);
      d              <= dbg_dat_o;  
      $display("%t %m  cycle %x %x",$realtime,a,dbg_dat_o );
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      next(1);          
    end
  endtask
  




// compare cycle
  task u_cmp;
    input   [31:0]  a;
    input  [31:0]   d_exp;
  
     begin
      dbg_adr_i      <=  a;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b1;
      exp_rdata      <=  d_exp;
      next(4);
      mask_rdata     <= 32'hffffffff;
      next(1);
      $display("%t %m  cycle %x %x",$realtime,a,d_exp );
      mask_rdata     <= 32'h00000000;
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      next(1);          
    end
  endtask