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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [verilog/] [tasks] - Rev 135

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task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);       
endtask


task clear_rx_host;
 begin
 rx_clr               <= 1'b1;
 next(1);
 rx_clr               <= 1'b0;
 end
endtask
   


 
task send_byte;
  input [7:0] byte_out;
   begin
   $display("%t %m %2h",$realtime ,byte_out  );
   tx_data  <= byte_out;
   next(1);
   tx_write   <= 1'b1;
   next(1);
   tx_write   <= 1'b0;
   next(1);
   while(busy)   next(1);
   mask_tx_ack_err <= 1'b1;
   next(1);
   mask_tx_ack_err <= 1'b0;
   end
endtask // send_byte




   
task rcv_byte;
  input [7:0] byte_in;
   begin
   exp_rcv_byte  <= byte_in;
   
   while(!rx_read)  next(1);
   $display("%t           checking    %h",$realtime,byte_in);
   mask_rcv_byte <= 8'hff;      
   next(1);
   mask_rcv_byte <= 8'h00;         
end
endtask
   

   

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