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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [code] - Rev 134

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assign drive_8 = 8'bzzzzzzzz;
assign drive_1 = 1'bz;

   

   
always@(posedge clk)
if(reset)   
  begin
  parity_enable         <= 1'b0;    
  txd_data_in           <= 8'h00;
  txd_parity            <= 1'b0;
  txd_force_parity      <= 1'b0;
  txd_load              <= 1'b0;
  txd_break             <= 1'b0;
  rxd_parity            <= 1'b0;
  rxd_force_parity      <= 1'b0;
  rxd_data_avail_stb    <= 1'b0;
  exp_rxd_stop_error    <= 1'b0;
  exp_rxd_parity_error  <= 1'b0;
  exp_rxd_data_out      <= 8'h00;
  mask_rxd_stop_error   <= 1'b0;
  mask_rxd_parity_error <= 1'b0;
  mask_rxd_data_out     <= 8'h00;     
  end

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