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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [tasks] - Rev 134

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task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);       
endtask

   


task clear_rx_host;
 begin
 next(1);
 end
endtask
   


 
task send_byte;
  input [7:0] byte_out;

   begin
   while(!txd_buffer_empty)   next(1);
   $display("%t %m         %2h",$realtime ,byte_out);
   txd_data_in  <= byte_out;
   next(1);
   txd_load   <= 1'b1;
   next(1);
   txd_load   <= 1'b0;
   next(1);
   end
endtask // send_byte



task rcv_byte;
  input [7:0] byte_in;
   begin
   exp_rxd_data_out     <= byte_in;
   while(!rxd_data_avail)  next(1);
   $display("%t %m checking %h",$realtime,byte_in); 
   mask_rxd_stop_error   <= 1'b1;
   mask_rxd_parity_error <= 1'b1;
   mask_rxd_data_out     <= 8'hff;     
   next(1);
   mask_rxd_stop_error   <= 1'b0;
   mask_rxd_parity_error <= 1'b0;
   mask_rxd_data_out     <= 8'h00;     
   rxd_data_avail_stb   <= 1'b1;
   next(1);
   rxd_data_avail_stb   <= 1'b0;
   next(1);            
end
endtask
   
    

      

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