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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [verilog/] [top.tasks] - Rev 131

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task next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);       
endtask




task wait_tx;

begin
  while(!txd_buffer_empty) next(1);
end
endtask // wait_tx

   

task send_byte;
  input [7:0] byte_out;

begin
  while(!txd_buffer_empty) next(1);
  $display("%t %m        %2h",$realtime ,byte_out  );
  txd_data_in  = byte_out;
  next(1);
  txd_load   = 1'b1;
  next(1);
  txd_load   = 1'b0;
  next(1);
end
endtask // send_byte


task rcv_byte;
  input [7:0] byte_in;
   begin
   exp_rx_shift_buffer <= byte_in;  
   while(!rx_frame_rdy)  next(1);
   $display("%t %m check   %h   %h ",$realtime,rx_shift_buffer,byte_in); 
   mask_rx_frame_err    <= 1'b1; 
   mask_rx_parity_err   <= 1'b1; 
   mask_rx_shift_buffer <= 8'hff;        
   next(1);
   mask_rx_frame_err    <= 1'b0; 
   mask_rx_parity_err   <= 1'b0; 
   mask_rx_shift_buffer <= 8'h00;        
end
endtask


   


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