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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Rev 134

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assign prb_device_rx_data = 8'h00;

assign  prb_device_rx_parity = 1'b0;

always@(posedge clk)
  if(reset)
   mask_device_rx_parity <= 1'b0;
  else
   mask_device_rx_parity <= 1'b0;

always@(posedge clk)
  if(reset)
   mask_device_rx_data <= 8'b0;
  else
   mask_device_rx_data <= 8'b0;



reg [23:0] red_h_cnt;
reg [23:0] green_h_cnt;
reg [23:0] blue_h_cnt;


reg [23:0] red_h_lat;
reg [23:0] green_h_lat;
reg [23:0] blue_h_lat;


reg [47:0] v_cnt;
reg [47:0] v_lat;

reg hsync;
reg vsync;



always@(posedge clk)
if(reset)             hsync <= 1'b0;
else                  hsync <= !hsync_n;


always@(posedge clk)
if(reset)             vsync <= 1'b0;
else                  vsync <= !vsync_n;




always@(posedge clk)
if(reset || (hsync))               red_h_cnt <= 24'h0;
else                               red_h_cnt <= red_h_cnt + red;

always@(posedge clk)
if   (reset)                       red_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       red_h_lat <= red_h_cnt;
else                               red_h_lat <= red_h_lat;

always@(posedge clk)
if(reset || (hsync))               green_h_cnt <= 24'h0;
else                               green_h_cnt <= green_h_cnt + green;

always@(posedge clk)
if   (reset)                       green_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       green_h_lat <= green_h_cnt;
else                               green_h_lat <= green_h_lat;

always@(posedge clk)
if(reset || (hsync))               blue_h_cnt <= 24'h0;
else                               blue_h_cnt <= blue_h_cnt + blue;

always@(posedge clk)
if   (reset)                       blue_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       blue_h_lat <= blue_h_lat;
else                               blue_h_lat <= blue_h_cnt;



always@(posedge clk)
if   (reset)                       v_cnt      <= 48'h0;
else if(!hsync_n &&(!hsync))       v_cnt      <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt;
else                               v_cnt      <= v_cnt;





always@(posedge clk)
if   (reset)                       v_lat <= 48'h0;
else if(!vsync_n &&(vsync))        v_lat <= v_cnt;
else                               v_lat <= v_lat;








/*
io_probe_in 
#(.MESG   ("vga data receive error"),
  .WIDTH  (8)
  )
rx_shift_buffer_prb   
(
  .clk           ( clk ),
  .expected_value( exp_rx_shift_buffer),
  .mask          ( mask_rx_shift_buffer),
  .signal        ( prb_rx_shift_buffer)
);      


io_probe_in
#(.MESG   ("vga parity error"))
rx_parity_err_prb   
(
  .clk           ( clk ),
  .expected_value( exp_rx_parity_err),
  .mask          ( mask_rx_parity_err),
  .signal        ( prb_rx_parity_err)
);      

*/


 







   

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