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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [src/] [geda/] [sym/] [clock_gen_def.sym] - Rev 133
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v 20100214 1
B 300 0 4000 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1250 5 10 1 1 0 0 1 1
device=clock_gen_def
T 400 -300 5 10 0 1 0 0 1 1
source=clock_gen_def.sch
T 400 1450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=BAD
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
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T 400 400 5 10 0 1 0 1 1 1
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}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=START
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=clock__master_clk
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
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P 4300 200 4600 200 4 0 1
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T 4200 200 5 10 1 1 0 7 1 1
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T 4200 200 5 10 0 1 0 7 1 1
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P 4300 400 4600 400 4 0 1
{
T 4200 400 5 10 1 1 0 7 1 1
pinnumber=FAIL
T 4200 400 5 10 0 1 0 7 1 1
pinseq=6
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P 4300 600 4600 600 10 1 1
{
T 4200 600 5 10 1 1 0 7 1 1
pinnumber=reset__master_reset
T 4200 600 5 10 0 1 0 7 1 1
pinseq=7
}
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