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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sym/] [micro_bus_model_def.sym] - Rev 135
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v 20100214 1B 300 0 2900 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1T 400 1650 5 10 1 1 0 0 1 1device=micro_bus_model_defT 400 1850 5 10 1 1 0 0 1 1refdes=U?T 400 2000 0 10 0 1 0 0 1 1vendor=opencores.orgT 400 2000 0 10 0 1 0 0 1 1library=TestbenchT 400 2000 0 10 0 1 0 0 1 1component=micro_bus_modelT 400 2000 0 10 0 1 0 0 1 1version=defP 300 200 0 200 4 0 1{T 400 200 5 10 1 1 0 1 1 1pinnumber=resetT 400 200 5 10 0 1 0 1 1 1pinseq=1}P 300 400 0 400 4 0 1{T 400 400 5 10 1 1 0 1 1 1pinnumber=clkT 400 400 5 10 0 1 0 1 1 1pinseq=2}P 3200 200 3500 200 10 1 1{T 3100 200 5 10 1 1 0 7 1 1pinnumber=wdata[7:0]T 3100 200 5 10 0 1 0 7 1 1pinseq=3}P 3200 400 3500 400 10 1 1{T 3100 400 5 10 1 1 0 7 1 1pinnumber=addr[addr_width-1:0]T 3100 400 5 10 0 1 0 7 1 1pinseq=4}P 3200 600 3500 600 10 1 1{T 3100 600 5 10 1 1 0 7 1 1pinnumber=rdata[7:0]T 3100 600 5 10 0 1 0 7 1 1pinseq=5}P 3200 800 3500 800 4 0 1{T 3100 800 5 10 1 1 0 7 1 1pinnumber=wrT 3200 800 5 10 0 1 0 7 1 1pinseq=6}P 3200 1000 3500 1000 4 0 1{T 3100 1000 5 10 1 1 0 7 1 1pinnumber=rdT 3200 1000 5 10 0 1 0 7 1 1pinseq=7}P 3200 1200 3500 1200 4 0 1{T 3100 1200 5 10 1 1 0 7 1 1pinnumber=csT 3200 1200 5 10 0 1 0 7 1 1pinseq=8}
