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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sym/] [mt45w8mw12_def.sym] - Rev 135
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v 20100214 1
B 300 0 3800 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2250 5 10 1 1 0 0 1 1
device=mt45w8mw12_def
T 400 2450 5 10 1 1 0 0 1 1
refdes=U?
T 400 2600 0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 2600 0 10 0 1 0 0 1 1
library=Testbench
T 400 2600 0 10 0 1 0 0 1 1
component=mt45w8mw12
T 400 2600 0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=addr[ADDR_BITS-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=we_n
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=ub_n
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=oe_n
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=lb_n
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=cre
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=ce_n
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=adv_n
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=dq[DQ_BITS-1:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=10
}
P 4100 400 4400 400 4 0 1
{
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=o_wait
T 4100 400 5 10 0 1 0 7 1 1
pinseq=11
}